Memory devices including blocking layers
US10490566B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2016 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Apr 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
A memory device includes a cell region and a peripheral circuit region adjacent the cell region. A plurality of gate electrode layers and insulating layers are stacked on the substrate in the cell region, and a plurality of circuit devices are in the peripheral circuit region. A first interlayer insulating layer is on the substrate in the peripheral circuit region and covers the plurality of circuit devices, and a second interlayer insulating layer is on the substrate in the cell region and the peripheral circuit region. A blocking layer is on the plurality of circuit devices between the first and second interlayer insulating layers. The blocking layer is on an upper surface, of the first interlayer insulating layer, and a side surface of the blocking layer is covered by the second interlayer insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.