Systems and methods providing a matching circuit that bypasses a parasitic impedance
US10491172B2 · kind B2 · utility
0Cited by
5References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2016 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Nov 23, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10166
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A circuit including a radio frequency (RF) amplifier including a transistor configured to receive an RF signal at its control terminal, a capacitor coupled to a first terminal of the transistor, an inductor coupled to a second terminal of the transistor, wherein the capacitor and inductor form a loop from the first terminal to the second terminal, wherein the loop bypasses a parasitic inductance between the second terminal and ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.