Semiconductor device including CMOS circuit and operation method thereof
US10491208B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2019 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Jan 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0027
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The inventive concept relates to a semiconductor device including a CMOS circuit and an operation method thereof. A semiconductor device according to an embodiment of the inventive concept includes a semiconductor circuit, a controller, and a voltage generator. The semiconductor circuit operates at a drive voltage to reduce the delay time between input and output as the temperature increases. The controller determines the malfunction of the CMOS circuit based on the difference between the source-drain current of the PMOS transistor and the source-drain current of the NMOS transistor as the temperature changes. The voltage generator generates or adjusts a body-bias voltage applied to the PMOS transistor or the NMOS transistor based on a malfunction determination of the controller. According to the inventive concept, malfunctions and performance deterioration occurring in a CMOS circuit operating at a low voltage may be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.