Injection locked frequency divider
US10491227B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2018 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Sep 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/32
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency divider includes a signal injection circuit and an oscillating circuit. The signal injection circuit includes a transistor of which a gate receives an input signal with an input frequency, a drain and a source cooperatively provide a first differential signal pair, and a body receives a biasing voltage. The two circuits cooperate to form a tank circuit having a free-running frequency and defining a frequency locking range which is around N times the free-running frequency and within which the input frequency falls. The tank circuit generates a second differential signal pair that is related to the first differential signal pair and that has an oscillating frequency which is one-Nth the input frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.