Multi-chip timing alignment to a common reference signal
US10496127B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2018 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Jun 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03J2200/11
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The subject technology provides for removing a source of delay in a phase-locked loop (PLL) by causing the output rising edge to occur at the same time as the input rising edge. The subject technology replicates the amount of delay experienced along an input reference signal path to the PLL as close as possible using a same circuit configuration and bias circuits as in the input reference signal path. For example, a timing alignment circuit containing a replica circuit adds compensation delay to a negative feedback loop signal to match the feedback loop delay with the reference path delay. The delay of the reference signal path is estimated and added into the replica circuit. The delay characteristics of these two paths negate one another such that the phases of the input reference signal and the feedback loop signal become phase-locked at the input to the PLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.