Method for reducing power consumption memory, and computer device
US10496303B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2017 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Jan 20, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing power consumption of a memory of a computer device is presented. The memory includes at least two channels, each channel includes at least two storage units, a dirty data storage area is set in the memory, and the dirty data storage area includes at least one storage unit in each channel. After the computer device encounters a power failure, a backup power supply is turned on to supply power to the memory, then the storage unit included in the dirty data storage area is kept in a normal operating state, and a storage unit outside the dirty data storage area in the memory is caused to enter a self-refreshing state. Data in the dirty data storage area is then written to a non-volatile storage area of the computer device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.