Patent · US Active

Register error detection system

US10496471B2 · kind B2 · utility

1Cited by

2References

15Claims

0Family size

Assignee

NXP USA, Inc. · US

Inventors

Andres Barrilado Gonzalez · Toulouse, FR
Ralf Reuter · Landshut, DE
Dominique Delbecq · Fonsorbes, FR
Francesco d'Esposito · Steenokkerzeel, BE
Arnaud Sion · Munich, DE
Gustavo Adolfo Guarin Aristizabal · Munich, DE
Marcel Welpot · Munich, DE

Key dates

Filing date	Sep 15, 2017
Grant date	Dec 3, 2019
Priority date	—
Expiry date	Mar 17, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system for register error detection is described, the system comprising: a plurality of addressable registers comprising sets of registers, the registers in each set having contiguous addresses; a cyclic redundancy check generator coupled to the addressable registers and configured to determine a cyclic-redundancy-check result for each set of registers from the values of each of the respective set of registers; a controller coupled to the registers and the cyclic-redundancy-check generator. The controller comprises a cyclic-redundancy-check calculator and is configured to determine an expected cyclic-redundancy-check result from expected values for each of the set of registers, to read the cyclic-redundancy-check result for each of the set of registers determined by the cyclic-redundancy-check generator, and to compare the generated cyclic-redundancy-check result with the calculated cyclic-redundancy-check result and wherein a difference between the generated cyclic-redundancy-check result and the calculated cyclic-redundancy-check result is indicative of an error condition.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.