System on chip and method of executing a process in a system on chip
US10496554B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2014 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Jan 16, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system on chip, comprising a processing unit for executing processes, a memory unit, and a memory control unit connected between the processing unit and the memory unit, is described. The memory control unit allocates a memory region to a process. The memory control unit comprises a process activity counter which counts a duration of the process or transactions by the process to or from the memory region and which maintains a process activity count representing the counted duration of the process or the counted transactions to or from the memory region. The memory control unit disables the memory region in response to the process activity count exceeding a maximum process activity count. Notably, it blocks the memory region against further transactions by the process and against transactions by any other processes.A method of operating a system on chip is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.