Display device
US10497335B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2017 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Jun 1, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display device comprises: a pixel array including pixels connected to gate lines; a gate driver that sequentially supplies scan signals to the gate lines by using a plurality of stages connected in cascade; and a driving voltage generator that supplies first and second driving voltages to the gate driver and inverts the first and second driving voltages of opposite phases at given intervals, wherein an nth stage (n is a natural number), among the stages of the gate driver, comprises: a start controller that charges a Q1 node in a period when an (n−1)th scan signal and a first clock signal are synchronized, and charges a Q1B node in a period when an (n−1)th carry signal, opposite in phase to the (n−1)th scan signal, and the first clock signal are synchronized; a first node controller that charges a Q2 node or a Q2B node in response to a voltage at the Q1 node; a first output control transistor that outputs an nth scan signal through a Q node in response to a voltage at the Q2 node; and a second output control transistor that charges the Q node with the second driving voltage in response to a voltage at the Q2B node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.