Method and circuit for self-training of a reference voltage and memory system including the same
US10497412B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2018 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Jul 3, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/4401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.