Memristor arrays in crossbars
US10497442B1 · kind B1 · utility
8Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2018 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Nov 15, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In example implementations, a memory cell is provided. The memory cell includes a plurality of row lines and a plurality of column lines. The plurality of row lines and the plurality of column lines intersect to form a 2×2 array. The memory cell may include a plurality of memristors. A memristor is coupled to each unique combination of a row line and a column line in the 2×2 array. An input line is coupled to a first row of memristors. An invert is coupled to the input line. An inverted input line from the inverter is coupled to the second row of memristors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.