Silicon-on-insulator structure having bipolar stress, and manufacturing method therefor

US10497718B2 · kind B2 · utility

Inventors

• Yanfei Ma · Carmel, US
• Changfeng Wang · Shanghai, CN
• Duanquan LIAO · Shanghai, CN

Key dates

• Filing date: May 17, 2018
• Grant date: Dec 3, 2019
• Expiry date: May 17, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/01
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Provided are a silicon-on-insulator structure having bipolar stress and a manufacturing method therefor. The manufacturing method comprises providing a composite substrate, wherein the composite substrate has a silicon substrate layer, a buried oxide layer and a silicon-on-insulator layer sequentially from bottom to top, epitaxially growing a silicon germanium layer on an upper surface of the silicon-on-insulator layer; depositing a hard mask layer to cover a portion of the silicon germanium layer corresponding to an N-type MOS transistor region; depositing a surface oxide layer to cover the silicon germanium layer and the hard mask layer; performing a high temperature annealing treatment so that a portion of the silicon-on-insulator layer corresponding to a P-type MOS transistor region is converted into a silicon-germanium-on-insulator layer, and the portion corresponding to the N-type MOS transistor region is converted into a tensile stress silicon-on-insulator layer.