Electronic device

US10497789B2 · kind B2 · utility

Assignee

• Technion Research & Development Foundation Limited · IL

Inventors

• Nir Tessler · Zichron Ya'akov, IL
• Ariel Jacques Ben Sasson · Haifa, IL
• Michael Greenman · Yoqneam Illit, IL

Key dates

• Filing date: Mar 27, 2018
• Grant date: Dec 3, 2019
• Expiry date: Apr 1, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10K10/84

Abstract

A transistor structure is configured as a vertical type transistor. The transistor structure has a patterned electrode located between a gate electrode and a channel region of the transistor structure. The patterned electrode has one or more regions of discontinuity of the electrode. The patterned source electrode has at least two layers having at least a first and second barriers for injection of charge carriers into the channel region. The patterned electrode is configured such that a second layer having a second, higher, barrier for injection of charge carriers is configured to provide a physical barrier for flow of charge carriers from the electrode into the channel region.