Multi-level inverter with synchronous rectification technology
US10498256B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2017 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Nov 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/537
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Provided is a multi-level inverter, which includes a first bus capacitor, a second bus capacitor, a third bus capacitor, a fourth bus capacitor, a seventh switch unit, an eighth switch unit, an inverter circuit and a filtering circuit. The first bus capacitor, the second bus capacitor, the third bus capacitor and the fourth bus capacitor are connected between a positive direct current bus and a negative direct current bus in series, and a series point between the second bus capacitor and the third bus capacitor is grounded. The switch transistor of the anti-parallel diode having small on-state resistance is used in the multi-level inverter, thereby reducing power loss of the switch unit in the multi-level inverter and reducing power consumption of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.