Comparator output circuitry for single slope analog to digital converter
US10498322B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 13, 2019 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Feb 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/123
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An output circuit for use with a comparator includes a first transistor having a control terminal coupled to receive an output signal from a first stage of the comparator. A second transistor is coupled between the first transistor and a reference voltage. The second transistor has a control terminal coupled to receive a first reset signal. The second transistor is coupled to precharge a first output node of the first transistor between the first and second transistors to the reference voltage prior to a comparison operation of the comparator. An output stage has an input node coupled to the first output node. The output stage is coupled to generate an output voltage of the output circuit at an output node of the output stage in response to the first output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.