Adaptive gate buffer for a power stage
US10498333B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2019 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Jan 30, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/575
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A circuit includes a first power transistor including a first control input and first and second current terminals. The circuit includes a second power transistor including a second control input and third and fourth current terminals. Third current terminal couples to the first current terminal, and the fourth current terminal couples to the second current terminal at an output node. An error amplifier generates an error signal based on a difference between a reference voltage and an output voltage on the output node. An adaptive buffer couples to an output of the error amplifier and couples to the first and second control inputs. The adaptive buffer causes the first power transistor to be on through a range of output current and to cause the second power transistor to be on through some, but not all, of the range of output current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.