Patent · US Active

Low density parity check decoder using binary logarithm and decoding method thereof

US10498363B2 · kind B2 · utility

3Cited by

1References

13Claims

0Family size

Assignee

KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY · KR

Inventors

Hyuk KIM · Daejeon, KR
Insan Jeon · Daejeon, KR

Key dates

Filing date	Nov 3, 2017
Grant date	Dec 3, 2019
Priority date	—
Expiry date	Mar 3, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH03M13/114
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Provided is a low density parity check (LDPC) decoder. An LDPC decoder according to an embodiment of the inventive concept includes a variable node calculator for adding an input log-likelihood ratio (LLR) to message information of a check node to output the added values, a check node calculator for extracting signs of the output values of the variable node calculator, determining a minimum value of the output values, and calculating a correction term for the output values by using a binary logarithm to transmit to the variable node calculator, a hard decision block for determining bit values of the output values of the variable node calculator, and a parity check block for performing a parity check operation for determining validity of the bit value.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.