Patent · US Active

On-chip jitter tolerance testing

US10498469B2 · kind B2 · utility

2Cited by

1References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Mor Cohen · Haifa, IL
Amir Mezer · Haifa, IL
Golan PERRY · Haifa, IL
Adee O. Ran · Ma'ayan Baruch, IL

Key dates

Filing date	May 21, 2018
Grant date	Dec 3, 2019
Priority date	—
Expiry date	May 21, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH04L43/50
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

In accordance with embodiments disclosed herein, there is provided systems and methods for on-chip jitter tolerance testing. A receiver component includes a clock data recovery (CDR) logic circuit. The CDR logic circuit includes a controller to receive a phase signal and to output a DCO control signal; jitter injection (JINJ) logic to generate a first jitter signal at a first frequency and a first amplitude; and digitally controlled oscillator (DCO) to receive the first jitter signal applied to the DCO control signal and to output, based on the first jitter signal applied to the DCO control signal, a first DCO clock signal for on-chip jitter tolerance testing.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.