Ramp signal settling reduction circuitry
US10498993B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2019 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Feb 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/123
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Comparison circuitry includes a comparator having a first input configured to receive a pixel signal. A switch is coupled to a second input of the comparator, a reference generator, and a ramp generator. A first capacitance is coupled to the switch. The switch is configured to couple the first capacitance to the reference generator to charge the first capacitance to a reference voltage from the reference generator prior to a ramp event in a ramp signal, and to couple the first capacitance to the ramp signal from the ramp generator at an onset of the ramp event in the ramp signal. The first capacitance is coupled to provide positive current injection into the ramp signal at the onset of the ramp event in the ramp signal to reduce a ramp settling time in the ramp signal, which is provided to the second input of the comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.