Noise reduction in digitizing systems
US10502763B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2016 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Aug 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed are systems and methods related to a noise reduction device employing an analog filter and a corresponding inverse digital filter. The combination and placement of the filters within the systems aids in reducing noise introduced by processing the signal. In some embodiments, the combination of filters may also provide for increased flexibility when de-embedding device under test (DUT) link attenuation at higher frequencies. Further, the filters are adjustable, via a controller, to obtain an increased signal to noise ratio (SNR) relative to a signal channel lacking the combination of filters. Additional embodiments may be disclosed and/or claimed herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.