Floating-point division alternative techniques
US10503473B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2018 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Jun 7, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5356
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed relating to circuitry configured to perform reciprocal-based floating-point division. In some embodiments, floating-point circuitry includes reciprocal circuitry configured to generate a reciprocal of a divisor, multiplication circuitry configured to multiply the reciprocal results with a dividend, and circuitry configured to clear a least significant bit of an integer representation of the multiplication output to generate a modified multiplication output. The floating-point circuitry may be configured to convert the modified multiplication output to a representation using the first precision to generate a division output. In some embodiments, the refinement using the integer representation may provide correctly-rounded subnormal division results. The disclosed techniques may improve accuracy, reduce processing time, and/or reduce instructions needed for floating-point division, with little to no increase in chip area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.