Context sensitive barriers with an implicit access ordering constraint for a victim context
US10503512B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2015 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | May 6, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1458
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for data processing and a method of data processing are provided, according to which the processing circuitry of the apparatus can access a memory system and execute data processing instructions in one context of multiple contexts which it supports. When the processing circuitry executes a barrier instruction, the resulting access ordering constraint may be limited to being enforced for accesses which have been initiated by the processing circuitry when operating in an identified context, which may for example be the context in which the barrier instruction has been executed. This provides a separation between the operation of the processing circuitry in its multiple possible contexts and in particular avoids delays in the completion of the access ordering constraint, for example relating to accesses to high latency regions of memory, from affecting the timing sensitivities of other contexts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.