Patent · US Active

Dynamic performance biasing in a processor

US10503550B2 · kind B2 · utility

1Cited by

9References

25Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Monica Gupta · Santa Clara, US
Russell J. Fenger · Beaverton, US
Vijay Dhanraj · Stuttgart, DE
Deepak Samuel Kirubakaran · Hillsboro, US
Srividya Ambale · Hillsboro, US
Israel Hirsh · Kiryat Motzkin, IL
Eliezer Weissmann · Haifa, IL
Hisham Abu Salah · Kiryat Shmona, IL

Key dates

Filing date	Sep 30, 2017
Grant date	Dec 10, 2019
Priority date	—
Expiry date	Oct 13, 2037

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Technologies are provided in embodiments to dynamically bias performance of logical processors in a core of a processor. One embodiment includes identifying a first logical processor associated with a first thread of an application and a second logical processor associated with a second thread, obtaining first and second thread preference indicators associated with the first and second threads, respectively, computing a first relative performance bias value for the first logical processor based, at least in part, on a relativeness of the first and second thread preference indicators, and adjusting a performance bias of the first logical processor based on the first relative performance bias value. Embodiments can further include increasing the performance bias of the first logical processor based, at least in part, on the first relative performance bias value indicating a first performance preference that is higher than a second performance preference.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.