Scheduler for vector processing operator readiness
US10503552B1 · kind B1 · utility
1Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Apr 28, 2017 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Jan 8, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a plurality of hardware engines and a scheduler circuit. The hardware engines may be configured to process a plurality of vectors using a plurality of operators. The scheduler circuit may be configured to (i) parse a directed acyclic graph into one or more of the operators, (ii) determine a readiness of each of the operators and (iii) schedule the one or more operators in at least one of the hardware engines based on the readiness. The scheduler circuit may be implemented solely in hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.