Time-based on-chip hardware performance monitor
US10503624B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2018 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Aug 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a distributed performance monitor circuit that includes a plurality of performance monitors connected to a cross-trigger network. Each performance monitor corresponds to a respective functional block of a system and includes a counter circuit. The counter circuit includes a programmable time window counter configured to determine an adjustable counting period, and an event counter configured to count a number of occurrences of an event occurring in the respective functional block during the counting period. The cross-trigger network is configured to receive an output trigger signal generated by a performance monitor when the number of occurrences of the event occurring in the corresponding functional block during the counting period is outside of a threshold band for the performance monitor, and send an input trigger signal to the plurality of performance monitors based on receiving the output trigger signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.