Cache coherence directory architecture with decoupled tag array and data array
US10503642B2 · kind B2 · utility
0Cited by
0References
10Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Aug 25, 2017 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Dec 26, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/604
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing method includes allocating a tag entry in a tag array for a data block; allocating a data entry in a data array for the data block when the data block is actively shared; and de-allocating the data entry when the data block is temporarily private or gets evicted in the data array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.