Patent · US Active

System and method for controlling phase alignment of clock signals

US10504569B2 · kind B2 · utility

0Cited by

1References

7Claims

0Family size

Assignee

INVECAS TECHNOLOGIES PVT. LTD · IN

Inventors

Gyan Prakash · Beaverton, US
Nidhir Kumar · Bengaluru, IN
Muniswara Reddy Vorugu · Chittoor, IN

Key dates

Filing date	Jun 30, 2016
Grant date	Dec 10, 2019
Priority date	—
Expiry date	Jun 30, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/091
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system and method for aligning clock signals in a DDR DRAM module is disclosed. The system includes a phase detector circuitry, a controllable delay circuit, a first delay circuit and a synchronizing circuit. A clock signal is simultaneously transmitted through the first delay circuit and the controllable delay circuit. Subsequently, the clock signals transmitted through the first delay circuit and the controllable delay circuit are captured at the output thereof, and fed as inputs to the phase detector circuitry. The phase detector circuitry determines whether the clock signals are in phase, and accordingly adjusts the delay associated with the controllable delay circuit until the two clock signals are determined to be in phase.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.