Fan-out semiconductor package
US10504825B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2018 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | May 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; first metal bumps disposed on the connection pads; second metal bumps disposed on an uppermost wiring layer of the wiring layers; an encapsulant covering at least portions of each of the frame, the semiconductor chip, and the first and second metal bumps and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads and the uppermost wiring layer through the first and second metal bumps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.