Semiconductor device
US10504846B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2018 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Feb 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphic data of a first wiring in a first area of a semiconductor wafer may be extracted, which may correspond to a semiconductor chip forming area. The first area may be surrounded by a scribed area of the semiconductor wafer. The first area includes a second area bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to a boundary between the first area and the second area. A first dummy pattern in the first area is laid out to have at least a first distance from the first wiring. A second dummy pattern in the second area is laid out to have at least the first distance from the first wiring and at least a third distance from the first dummy pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.