Structures and methods for providing electrical isolation in semiconductor devices
US10504874B2 · kind B2 · utility
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20Claims
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Assignee
Inventors
Key dates
| Filing date | Aug 1, 2016 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Aug 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/381
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor package structures and methods of forming the same are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.