Thin film transistor array panel
US10504927B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 10, 2016 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Dec 10, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/13306
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprises a multi-layered structure disposed over a substrate (101) and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer (105-1) disposed over the substrate (101) and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the lower sub-layer (105-1) substantially defining a first indium to zinc content ratio; a middle sub-layer (105-2) disposed over the lower sub-layer (105-1) and comprising a metal material; an upper sub-layer (105-3) disposed over the middle sub-layer (105-2) and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer (105-3) substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer (105-2).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.