Tri-layer semiconductor stacks for patterning features on solar cells

US10505068B2 · kind B2 · utility

Assignee

• SUNPOWER CORPORATION · US

Inventors

• Kieran Mark Tracy · San Jose, US
• David D. Smith · Dublin, US
• Venkatasubramani Balu · Santa Clara, US
• Asnat Masad · Mountain View, US
• Ann Waldhauer · La Honda, US

Key dates

• Filing date: Feb 25, 2019
• Grant date: Dec 10, 2019
• Expiry date: Feb 25, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10F77/703

Abstract

Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.