High resolution attenuator or phase shifter with weighted bits
US10505511B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2018 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Jul 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2210/036
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.