Flip-flop with a metal programmable initialization logic state
US10505522B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2018 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Oct 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/975
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A standard cell layout for a flip-flop includes a flip-flop circuit and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the flip-flop. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the flip-flop circuit for configuration programming of the flip-flop as an initialization in reset device (assertion of an initialization signal causing the flip-flop data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the flip-flop circuit for configuration programming of the flip-flop as an initialization in set device (assertion of the initialization signal causing the flip-flop data output to be set).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.