Input termination circuits for high speed receivers
US10505766B1 · kind B1 · utility
1Cited by
0References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2019 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Mar 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/20
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to communication systems and electrical circuits. According to an embodiment, an input termination circuit includes a first attenuation resistor and a second attenuation resistor. The resistance values of these two resistors are adjusted in opposite directions to maintain a stable output impedance. There are other embodiments as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.