Patent · US Active

Observation by a debug host with memory model and timing offset calculation between instruction and data traces of software execution carried on in a debug target having a main memory and a cache arrangement

US10509713B2 · kind B2 · utility

1Cited by

4References

18Claims

0Family size

Assignee

Telefonaktiebolaget LM Ericsson (Publ) · SE

Inventors

Peter Svensson · carrer de Sertori, SE
Bengt Wikenfalk · Helsingborg, SE

Key dates

Filing date	Aug 18, 2015
Grant date	Dec 17, 2019
Priority date	—
Expiry date	Sep 29, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/3648
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method, performed in a debug host, for observing software execution on a computer having one or more processor cores, a cache attached to the one or more processor cores via respective execution pipelines forming a cache arrangement, and a memory, comprises obtaining an instruction trace of the cache arrangement and a data trace for data being loaded from the memory into the cache. The instruction trace is synchronized with the data trace to generate a synchronized data trace and/or a synchronized instruction trace. A state of a memory model, representing a memory readable by the one or more processor cores via a respective instruction is updated using the synchronized data trace and the synchronized instruction trace.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.