Techniques to perform memory indirection for memory architectures
US10509728B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2017 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | Jan 25, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments are generally directed to an apparatus, method and other techniques to receive a request from a core, the request associated with a memory operation to read or write data, and the request comprising a first address and an offset, the first address to identify a memory location of a memory. Embodiments include performing a first iteration of a memory indirection operation comprising reading the memory at the memory location to determine a second address based on the first address, and determining a memory resource based on the second address and the offset, the memory resource to perform the memory operation for the computing resource or perform a second iteration of the memory indirection operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.