Accelerator for processing data
US10509846B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2017 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | Feb 8, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An accelerator for increasing the processing speed of a processor. The accelerator operates in two distinct modes. In a first mode for dense layer processing, row data sets and column data sets are sent to a multiplier for multiplication. In a second mode for sparse layer processing compressed row data sets are received by a row multiplexer and compressed column data sets are received by a column multiplexer. Each multiplexer is configured to compare the indexes of data sets with one another to determine matching indexes. When indexes match, the matching data sets are selected and sent to the multiplier for multiplication. When indexes do not match, data sets are stored in memory devices for subsequent cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.