Soft-verify write assist circuit of resistive memory and operating method thereof
US10510406B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2018 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | Oct 23, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operating method of the soft-verify write assist circuit of the resistive memory provides a voltage level applying step, a write operating step and a write voltage controlling step. The voltage level applying step is for applying a plurality of voltage levels to the reference voltage, the word line and the switching signal, respectively. The write operating step is for driving the memory cell to perform in a set process or a reset process via the first three-terminal switching element, the second three-terminal switching element and the soft-verify controlling unit during a write operation. The write voltage controlling step is for controlling the write voltage to be increased in the ramping cycle and decreased in the soft-verify cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.