Fan-out semiconductor package
US10511080B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2018 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | May 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01Q1/242
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fan-out semiconductor package includes: a core member including a plurality of insulating layers and a plurality of wiring layers and having a blind cavity penetrating through a portion of the plurality of insulating layers; a semiconductor chip disposed in the blind cavity; an encapsulant encapsulating at least portions of the core member and an active surface of the semiconductor chip and filling at least portions of the blind cavity; and a connection member disposed on the core member and an active surface of the semiconductor chip and including a redistribution layer connected to the connection pads. The plurality of wiring layers include antenna patterns and ground patterns, the antenna patterns and the ground patterns are disposed on different levels, and the antenna patterns are connected to the connection pads through the redistribution layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.