Metastable-free output synchronization for multiple-chip systems and the like
US10511312B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2019 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | Jun 28, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A chip having output synchronization includes a phase detector for receiving an external reference clock signal, an input delay path coupled to an output of the phase detector and having an output for providing an internal reference clock signal, an output delay path coupled to the output of the input delay path and having an output coupled to a feedback input of the phase detector, a phase adjustment circuit having a first input coupled to the output of the input delay path, a second input for receiving a local clock signal, and an output coupled to the control input of the input delay path, and a synchronization capture circuit having a first input coupled to the output of said input delay path, a second input for receiving the local clock signal, a third input for receiving a synchronization signal, and an output for providing a synchronization trigger signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.