Waveguide formation using CMOS fabrication techniques

US10514504B2 · kind B2 · utility

Assignee

• Massachusetts Institute of Technology · US

Inventors

• Jason S. Orcutt · Katonah, US
• Karan Mehta · Cambridge, US
• Rajeev Ram · Arlington, US
• Amir H. Atabaki · Brookline, US

Key dates

• Filing date: Feb 22, 2018
• Grant date: Dec 24, 2019
• Expiry date: Feb 22, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G02F1/0151
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer. Filling the trench with a high-index dielectric material yields a waveguide that can guide visible and/or infrared light, depending on the waveguide's dimensions and refractive index contrast.