Metastable true random number generator realized on FPGA
US10514894B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2018 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Jul 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/84
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A metastable true random number generator realized on an FPGA comprises a configurable delay chain including rough adjustment module and a fine adjustment module. The rough adjustment module comprises 32 rough adjustment cells each including a 1st 6-input lookup table and a two-to-one selector. The 1st input port of each 1st 6-input lookup table is connected to the 1st input terminal of the corresponding two-to-one selector, and the connecting terminal is the input terminal of the corresponding rough adjustment cell. The 2nd input port, the 3rd input port, the 4th input port, the 5th input port and the 6th input port of each 1st 6-input lookup table are all accessed to a low level 0. The output port of each 1st 6-input lookup table is connected to the 2nd input terminal of the corresponding two-to-one selector. The metastable true random number generator has the advantages of being capable of well counteracting inherent delay deviations, high in automation degree and high in output rate and having an operating point not prone to deviation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.