Updating aging information using second-level address translation for virtual address-backed virtual machines
US10515019B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2018 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Sep 4, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/651
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Updating aging information for memory backing a virtual address-backed virtual machine (VM). A virtual memory address (VA) is allocated, within a page table entry (PTE), to a process backing the VM. Based on memory access(es) by the VM to a non-mapped guest-physical memory address (GPA), the GPA is identified as being associated with the VA; an HPA is allocated for the accessed GPA; a host-physical memory address (HPA) is associated with the VA within the PTE; the GPA is associated with the HPA within a second level address translation (SLAT) structure entry; and an accessed flag is set within the SLAT entry. Aging information is updated, including identifying the SLAT entry; querying a value of the accessed flag in the SLAT entry; clearing the accessed flag in the SLAT entry without invalidating the SLAT entry; and updating aging information for the VA and/or HPA based on the queried value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.