Asymmetric transmission (TX) and receive (RX) lanes in a point-to-point interconnect using a peripheral component interconnect express (PCIE) resources in a computer system
US10515032B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2016 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Jul 1, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a host processor (105) and a peripheral device (708). The host processor (105) is coupled to the peripheral device (708) by a Peripheral Component Interconnect Express (PCIe) compliant link. The peripheral device (708) can include logic circuitry to identify, based on an application using the device and the host processor (105), a read to write ratio utilized by the application; and provide the read to write ratio to the host processor (105). The host processor (105) comprising logic circuitry to send a command signal to a device in communication with the hardware processor across a peripheral component interconnect express (PCIe) compliant link, the command signal indicating a transmission (TX) lane to receive (RX) lane ratio, the TX lane to RX lane ratio corresponding to the read to write ratio identified by the peripheral device (708); and receive an indication that the device is capable of supporting asymmetric TX and RX ratios.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.