Bit manipulation capable direct memory access
US10515036B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Oct 24, 2018 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Oct 24, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/2806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory management circuit includes a direct memory access (DMA) channel. The DMA channel includes logic configured to receive a buffer of data to be written using DMA. The DMA channel further includes logic to perform bit manipulation in real-time during a DMA write cycle of the first buffer of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.