Method, system, and computer program product for implementing routing aware placement or floor planning for an electronic design
US10515177B1 · kind B1 · utility
11Cited by
14References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2017 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Jan 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are techniques for implementing routing aware floorplanning or placement for an electronic design. These techniques preprocess an electronic design and a plurality of inputs for a floorplanner or placer, identify a tentative location for inserting a block comprising one or more pins into a floorplan or placement layout, snap the block to a legal location based at least in part upon one or more characteristics of the one or more pins or one or more pseudo-pins, and update the floorplan or placement layout with one or more geometric routes based in part or in whole upon the legal location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.