Patent · US Active

Method, system, and computer program product to implement snapping for an electronic design

US10515180B1 · kind B1 · utility

6Cited by

11References

22Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Karun Sharma · Fremont, US
Henry Yu · Palo Alto, US
John Hainsworth · Pittsburgh, US
Kuoching Lin · San Jose, US
Jeff Taraldson · San Ramon, US
Hui Xu · Lo Wu, CN

Key dates

Filing date	Dec 30, 2016
Grant date	Dec 24, 2019
Priority date	—
Expiry date	Nov 26, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06T3/60
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed is an approach to implement snapping techniques that aid the interactive, assisted, or automatic placement of layout instances or groups of layout instances for generating a legal placement layout while reducing or entirely eliminating any subsequent or separate performance of design rule checking with respect to the relevant design rules, constraints, or requirements governing the legality of the instances or groups of instances placed in the placement layout.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.