Apparatus for sampling electrical signals with improved hold time and associated methods
US10515708B2 · kind B2 · utility
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14References
20Claims
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Key dates
| Filing date | Aug 14, 2017 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Aug 14, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/161
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch to provide an input signal that is to be sampled, and a second switch coupled to receive the sampled signal. The second switch is further coupled to a capacitor. The S/H circuit further includes at least one native transistor coupled to the second switch and to the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.