Three-dimensional semiconductor devices with inclined gate electrodes
US10515979B2 · kind B2 · utility
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8References
20Claims
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Key dates
| Filing date | Aug 31, 2017 |
| Grant date | Dec 24, 2019 |
| Priority date | — |
| Expiry date | Aug 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional semiconductor device includes a substrate including a cell array region and a contact region, a stack structure including gate electrodes sequentially stacked on the substrate, vertical structures penetrating the stack structure, and cell contact plugs connected to end portions of the gate electrodes in the contact region. Upper surfaces of the end portions of the gate electrodes have an acute angle with respect to an upper surface of the substrate in the cell array region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.